1. Field of the Invention
The present invention relates to semiconductor chips and semiconductor devices of chip-on-chip structure in which semiconductor chips are bonded to each other in a stacked relation.
2. Description of Related Art
In general, interconnections provided in a semiconductor chip are composed of alloys such as of aluminum and copper for cost reduction. The interconnections of aluminum/copper-based alloy are susceptible to oxidation due to humidity. In this respect, a surface of an insulating film formed with the interconnections is covered with a surface protective film such as of silicon nitride.
For connection of the interconnections to a lead frame, portions of the interconnections are exposed from the surface protective film by forming openings in the surface protective film, and the exposed portions are connected to external terminals by lead-bonding with the use of Au (gold) wires. By the lead-bonding, pad surfaces are covered with end portions of the Au wires.
However, if the portions of the interconnections exposed through the openings of the surface protective film are partly left uncovered due to unsatisfactory lead bonding, the uncovered portions are liable to be oxidized and corroded by moisture.
In the case of semiconductor chips to be applied to a semiconductor device of chip-on-chip structure, for example, pad openings are formed in a surface thereof for partly exposing internal interconnections thereof. Bumps are provided on portions of the internal interconnections exposed through the pad openings. The internal interconnections of one of the semiconductor chips are electrically connected to the internal interconnections of the other semiconductor chip by bonding the opposed bumps of the respective semiconductor chips to each other. In this case, if the bumps are connected to the pad openings in an offset relation, the interconnections are partly exposed, and the exposed interconnection portions are susceptible to oxidation.
Another problem associated with the conventional semiconductor chips is that the interconnections generally have a reduced thickness for reduction of the chip thickness thereby to have a greater wiring resistance.
In the semiconductor chips for the semiconductor device of chip-on-chip structure, the pad openings for partly exposing the internal interconnections should be located in association with the bumps of the opposed semiconductor chip. That is, it is impossible to form the pad openings in positions independent of the positions of the bumps of the opposed semiconductor chip. This poses limitations on flexibility in layout of the interconnections and functional devices, thereby hindering further size reduction and integration of the semiconductor device.
It is a first object of the present invention to provide a semiconductor chip and a semiconductor device of chip-on-chip structure which are constructed so that interconnections thereof can be protected from corrosion.
It is a second object of the present invention to provide a semiconductor chip which features a reduced wiring resistance.
It is a third object of the present invention to provide a semiconductor device of chip-on-chip structure and a semiconductor chip which feature an increased flexibility in layout of pad openings for size reduction and higher integration thereof.
The semiconductor chip according to the present invention comprises: a semiconductor substrate; a surface protective film covering the semiconductor substrate; and an interconnection having a portion exposed on the surface protective film, at least the exposed portion of the interconnection being composed of an oxidation-resistant metal material.
The oxidation-resistant metal material is a material which is more oxidation-resistant than the other unexposed portion of the interconnection.
The interconnection may comprise an internal interconnection at least partly exposed from the surface protective film, and a metal coating film of the oxidation-resistant metal material covering a surface portion of the internal interconnection exposed from the surface protective film.
With this arrangement, the surface portion of the internal interconnection is covered with the metal coating film of the metal material which is more oxidation-resistant than the internal interconnection, so that the internal interconnection is not susceptible to corrosion due to oxidation thereof. The metal coating film covering the surface portion of the internal interconnection also serves to carry an electric current, so that the interconnection totally have a reduced resistance with a greater cross sectional area.
The internal interconnection may be exposed from the surface protective film through an opening formed in the surface protective film. In this case, the metal coating film preferably covers a surface of the internal interconnection exposed from the surface protective film through the opening.
With this arrangement, the surface of the interconnection exposed through the opening is covered with the metal coating film thereby to be insusceptible to corrosion due to oxidation thereof.
It is noted that the opening may be formed so that the surface of the interconnection is exposed either entirely or partly.
The internal interconnection may have an exposed surface which is flush with a surface of the surface protective film, and the metal coating film may cover the exposed surface of the internal interconnection.
In this case, the exposed surface of the internal interconnection which is flush with the surface protective film may be formed by covering the internal interconnection with the surface protective film and then polishing the surface protective film for planarization thereof.
With this arrangement, the surface protective film is planarized, so that the metal coating film which covers the surface of the internal interconnection exposed from the surface protective film can advantageously be formed by patterning through the photolithography technique.
The internal interconnection may project from the surface of the surface protective film. In this case, the metal coating film preferably covers surfaces (upper and side surfaces) of the internal interconnection projecting from the surface protective film.
With this arrangement, the surfaces of the internal interconnection projecting from the surface protective film are covered with the metal coating film. Therefore, there is no need to provide a protective film for protecting the interconnection even if the internal interconnection projects from the surface protective film.
The interconnection may be a surface interconnection of the oxidation-resistant metal material provided on the surface protective film.
In this case, the surface protective film may cover an internal interconnection and be formed with a pad opening for partly exposing the internal interconnection. Further, the surface interconnection may electrically be connected to the internal interconnection through the pad opening.
Where the semiconductor chip having the aforesaid construction is applied to a semiconductor device of chip-on-chip structure, electrical connection between the semiconductor chips can be achieved by bonding the surface interconnection of the semiconductor chip to a bump or the like of the opposed semiconductor chip. Thus, formation of the pad opening can be achieved without consideration of the position of the bump on the opposed semiconductor chip. This increases flexibility in layout of interconnections and functional devices, thereby allowing for size reduction and higher integration of the semiconductor chip.
Further, there is no need to give a consideration to the corrosion of the surface interconnection due to oxidation because the surface interconnection is composed of the oxidation-resistant metal material. Therefore, the need for formation of a protective film for protection of the surface interconnection is obviated. Accordingly, the semiconductor chip can be produced through a reduced number of process steps as compared with a case where a multi-level interconnection structure is employed to provide an increased number of internal interconnections. That is, the surface interconnection can be used in place of one of the internal interconnections of the multi-level interconnection structure.
The semiconductor chip may further comprise a bump formed by depositing a seed film on the surface of the surface protective film formed with the pad opening and selectively plating a portion of the seed film in the pad opening. In this case, the surface interconnection may be formed by patterning the seed film.
With this arrangement, the formation of the surface interconnection can be achieved by selectively removing the seed film for patterning thereof, for example, after the bump is formed by utilizing part of the seed film. Therefore, there is no need to separately prepare the material for the surface interconnection. Thus, a cost increase due to the provision of the surface interconnection can be suppressed.
The surface interconnection and the bump are preferably composed of the same material. This permits the surface interconnection and the bump to be formed in the same process step, thereby simplifying the production process.
The semiconductor device of chip-on-chip structure according to the present invention comprises: a first semiconductor chip which includes an interconnection having a portion exposed from a surface protective film thereof, at least the exposed portion of the interconnection being composed of an oxidation-resistant metal material; and a second semiconductor chip stacked on the first semiconductor chip and bonded to a surface of the first semiconductor chip, the second semiconductor chip having an inter-chip connector (interconnection connector) provided in a surface thereof opposed to the first semiconductor chip and electrically connected to an internal interconnection thereof. The interconnection of the first semiconductor chip is connected to the inter-chip connector of the second semiconductor chip for electrical connection between the first and second semiconductor chips.
The inter-chip connector may be a bump or a surface interconnection provided on an exposed portion of the internal interconnection of the second semiconductor chip. The interconnection of the first semiconductor chip may include an internal interconnection at least partly exposed from the surface protective film, and a metal coating film of the oxidation-resistant metal material covering a surface portion of the internal interconnection exposed from the surface protective film.
With this arrangement, the exposed portion of the internal interconnection of the first semiconductor chip is covered with the metal coating film, and the bump is provided on the exposed portion of the interconnection of the second semiconductor chip. Therefore, the interconnections of the first and second semiconductor chips are not susceptible to corrosion due to oxidation thereof.
With the bump provided on the interconnection of the second semiconductor chip, there is no need for formation of a bump on the first semiconductor chip. Therefore, the step of forming the bump on the first semiconductor chip can be obviated, thereby simplifying a semiconductor device production process.
In addition, where the surface of the metal coating film is recessed with respect to the surface of the surface protective film, the metal coating film of the first semiconductor chip is boned to the bump of the second semiconductor chip in depression-projection engagement. Thus, the first semiconductor chip can properly be positioned with respect to the second semiconductor chip for proper electrical connection between the first and second semiconductor chips.
The interconnection of the first semiconductor chip may be a surface interconnection of the oxidation-resistant metal material formed on the surface protective film.
The surface protective film may cover an internal interconnection and be formed with a pad opening for partly exposing the internal interconnection. In this case, the surface interconnection is preferably electrically connected to the internal interconnection through the pad opening.
The inter-chip connector may be a surface interconnection electrically connected to the internal interconnection of the second semiconductor chip via a pad opening of the second semiconductor chip. Alternatively, the inter-chip connector may be a bump provided on a portion of the internal interconnection exposed through the pad opening of the second semiconductor chip.
The term xe2x80x9csurface interconnectionxe2x80x9d herein means an interconnection extending on the surface of the semiconductor chip from the pad opening, and the term xe2x80x9cbumpxe2x80x9d herein means a projection projecting above the pad opening.
With this arrangement, the first semiconductor chip and the second semiconductor chip are electrically connected to each other by connecting the surface interconnection of the first semiconductor chip and the internal interconnection of the second semiconductor chip via the inter-chip connector. In other words, the surface interconnection of the first semiconductor chip is formed by patterning so as to allow for connection between the surface interconnection and the inter-chip connector for the electrical connection between the first semiconductor chip and the second semiconductor chip. Therefore, the position of the pad opening of the first semiconductor chip can be determined irrespective of the position of the pad opening of the second semiconductor chip. This increases flexibility in layout of the internal interconnection and functional devices in the first semiconductor chip, thereby allowing for further size reduction and integration of the semiconductor device.
Where the inter-chip connector is the surface interconnection, the pad openings of the first semiconductor chip and the second semiconductor chip can be located in positions independent of the positions of the pad openings of the second semiconductor chip and the first semiconductor chip, respectively. This increases flexibility in layout of the internal interconnections and functional devices in the first and second semiconductor chips, thereby allowing for further size reduction and integration of the first and second semiconductor chips.